View 5164405A_290375.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HM5164405A Series HM5165405A Series
16777216-word x 4-bit Dynamic Random Access Memory
ADE-203-459 (Z) Preliminary Rev. 0.3 Jan. 22, 1997 Description
The Hitachi HM5164405A Series, HM5165405A Series are CMOS dynamic RAMs organized 16,777,216word x 4-bit. They employ the most advanced CMOS technology for high performance and low power. The HM5164405A Series, HM5165405A Series offer Extended Data Out (EDO) Page Mode as a high speed access mode. They have the package variations of standard 400-mil 32-pin plastic SOJ and standard 400-mil 32-pin plastic TSOPII.
Features
* Single 3.3 V (0.3 V) * High speed Access time: 50 ns/60 ns/70 ns (max) * Low power dissipation Active mode : TBD/396 mW/342 mW (max) (HM5164405A Series) : TBD/576 mW/504 mW (max) (HM5165405A Series) Standby mode : 7.2 mW (max) : TBD (L-version) * EDO page mode capability * Refresh cycle 8192 RAS-only refresh cycles: 64 ms (HM5164405A Series) 4096 CBR/Hidden refresh cycles: 64ms : 128 ms (L-version) 4096 RAS-only refresh cycles: 64 ms (HM5165405A Series) 4096 CBR/Hidden refresh cycles: 64ms : 128 ms (L-version)
Preliminary: This document contains information on a new product. Specifications and information contained herein are subject to change without notice.
HM5164405A Series, HM5165405A Series
* 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) * Battery backup operation (L-version)
Ordering Information
Type No. HM5164405AJ-5 HM5164405AJ-6 HM5164405AJ-7 HM5164405ALJ-5 HM5164405ALJ-6 HM5164405ALJ-7 HM5165405AJ-5 HM5165405AJ-6 HM5165405AJ-7 HM5165405ALJ-5 HM5165405ALJ-6 HM5165405ALJ-7 HM5164405ATT-5 HM5164405ATT-6 HM5164405ATT-7 HM5164405ALTT-5 HM5164405ALTT-6 HM5164405ALTT-7 HM5165405ATT-5 HM5165405ATT-6 HM5165405ATT-7 HM5165405ALTT-5 HM5165405ALTT-6 HM5165405ALTT-7 Access time 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 400-mil 32-pin plastic TSOP II (TTP-32DC) Package 400-mil 32-pin plastic SOJ (CP-32DC)
2
HM5164405A Series, HM5165405A Series
Pin Arrangement
HM5164405AJ/ALJ Series
HM5164405ATT/ALTT Series
VCC I/O0 I/O1 NC NC NC NC WE RAS A0 A1 A2 A3 A4 A5 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
V SS I/O3 I/O2 NC NC NC CAS OE A12 A11 A10 A9 A8 A7 A6 V SS
VCC I/O0 I/O1 NC NC NC NC WE RAS A0 A1 A2 A3 A4 A5 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
V SS I/O3 I/O2 NC NC NC CAS OE A12 A11 A10 A9 A8 A7 A6 V SS
(Top view)
(Top view)
Pin Description
Pin name A0 to A12 Function Address input -- Row/Refresh address A0 to A12 -- Column address A0 to A10 Data input/Data output Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground No connection
I/O0 to I/O3 RAS CAS WE OE VCC VSS NC
3
HM5164405A Series, HM5165405A Series
Pin Arrangement
HM5165405AJ/ALJ Series
HM5165405ATT/ALTT Series
VCC I/O0 I/O1 NC NC NC NC WE RAS A0 A1 A2 A3 A4 A5 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
V SS I/O3 I/O2 NC NC NC CAS OE NC A11 A10 A9 A8 A7 A6 V SS
VCC I/O0 I/O1 NC NC NC NC WE RAS A0 A1 A2 A3 A4 A5 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
V SS I/O3 I/O2 NC NC NC CAS OE NC A11 A10 A9 A8 A7 A6 V SS
(Top view)
(Top view)
Pin Description
Pin name A0 to A11 Function Address input -- Row/Refresh address A0 to A11 -- Column address A0 to A11 Data input/Data output Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground No connection
I/O0 to I/O3 RAS CAS WE OE VCC VSS NC
4
HM5164405A Series, HM5165405A Series
Block Diagram (HM5164405A Series)
RAS
CAS
WE
OE
Timing and control
A0 A1 to A10 * * * Column address buffers
Column decoder
16M array
16M array Row decoder * * * I/O buffers 16M array I/O0 to I/O3
Row address buffers
16M array
A11 A12
5
HM5164405A Series, HM5165405A Series
Block Diagram (HM5165405A Series)
RAS
CAS
WE
OE
Timing and control
A0 A1 to A11 * * * Column address buffers
Column decoder
16M array
16M array Row decoder * * * I/O buffers 16M array I/O0 to I/O3
Row address buffers
16M array
6
HM5164405A Series, HM5165405A Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -0.5 to VCC + 0.5 ( 4.6 V (max)) -0.5 to +4.6 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Input high voltage Input low voltage Note: Symbol VCC VIH VIL Min 3.0 2.0 -0.3 Typ 3.3 -- -- Max 3.6 VCC + 0.3 0.8 Unit V V V Notes 1, 2 1 1
1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
7
HM5164405A Series, HM5165405A Series
DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) (HM5164405A Series)
HM5164405A -5 Parameter Operating current* , * 2
1
-6
-7
Symbol Min Max Min Max Min Max Unit Test conditions I CC1 I CC2 -- -- TBD -- TBD -- 110 -- 2 -- 95 2 mA t RC = min mA TTL interface RAS, CAS = VIH Dout = High-Z mA CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z
Standby current
--
TBD --
1
--
1
Standby current (L-version) RAS-only refresh current*2 Standby current*
1
I CC2
--
TBD --
TBD --
TBD A
I CC3 I CC5 I CC6 I CC7 I CC10
-- -- -- -- --
TBD -- TBD -- TBD -- TBD -- TBD --
110 -- 5 --
95 5
mA t RC = min mA RAS = VIH, CAS = VIL Dout = enable
CAS-before-RAS refresh current EDO page mode current*1, * 3 Battery backup current* (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage
4
140 -- 105 -- TBD --
120 mA t RC = min 90 mA t HPC = min CMOS interface Dout = High-Z, CBR refresh: tRC = 31.3 s t RAS 0.3 s CMOS interface RAS, CAS 0.2 V Dout = High-Z 0 V Vin VCC + 0.3 0 V Vin VCC Dout = disable High Iout = -2 mA Low Iout = 2 mA
TBD A
I CC11
--
TBD --
TBD --
TBD A
I LI I LO VOH VOL
TBD TBD -10 10 TBD TBD -10 10 TBD TBD 2.4 TBD TBD 0
-10 10 -10 10
A A
VCC 2.4 0.4 0
VCC V 0.4 V
Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less within one page mode cycle tHPC . 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V.
8
HM5164405A Series, HM5165405A Series
DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) (HM5165405A Series)
HM5165405A -5 Parameter Operating current* , * 2
1
-6
-7
Symbol Min Max Min Max Min Max Unit Test conditions I CC1 I CC2 -- -- TBD -- TBD -- 160 -- 2 -- 140 mA t RC = min 2 mA TTL interface RAS, CAS = VIH Dout = High-Z mA CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z
Standby current
--
TBD --
1
--
1
Standby current (L-version) RAS-only refresh current*2 Standby current*
1
I CC2
--
TBD --
TBD --
TBD A
I CC3 I CC5 I CC6 I CC7 I CC10
-- -- -- -- --
TBD -- TBD -- TBD -- TBD -- TBD --
160 -- 5 --
140 mA t RC = min 5 mA RAS = VIH, CAS = VIL Dout = enable
CAS-before-RAS refresh current EDO page mode current*1, * 3 Battery backup current* (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage
4
140 -- 120 -- TBD --
120 mA t RC = min 105 mA t HPC = min TBD A CMOS interface Dout = High-Z, CBR refresh: tRC = 31.3 s t RAS 0.3 s CMOS interface RAS, CAS 0.2 V Dout = High-Z 0 V Vin VCC + 0.3 V 0 V Vin VCC Dout = disable High Iout = -2 mA Low Iout = 2 mA
I CC11
--
TBD --
TBD --
TBD A
I LI I LO VOH VOL
TBD TBD -10 10 TBD TBD -10 10 TBD TBD 2.4 TBD TBD 0
-10 10 -10 10
A A
VCC 2.4 0.4 0
VCC V 0.4 V
Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less within one page mode cycle tHPC . 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V.
9
HM5164405A Series, HM5165405A Series
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS and CAS = VIH to disable Dout.
10
HM5164405A Series, HM5165405A Series
AC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) *1, *2, *3,*18
Test Conditions * * * * * Input rise and fall time: 2 ns Input levels: VIL = 0 V, V IH = 3 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5164405A/HM5165405A -5 Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Symbol Min Max t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT TBD -- TBD -- TBD -- TBD TBD TBD TBD TBD -- TBD -- TBD -- TBD -- TBD TBD TBD TBD TBD -- TBD -- TBD -- TBD -- TBD -- TBD -- TBD TBD -6 Min Max 104 -- 40 10 60 10 0 10 0 10 20 15 15 48 5 15 0 0 2 -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- -- -- -- 50 -7 Min Max 124 -- 50 13 70 13 0 10 0 13 20 15 18 58 5 18 0 0 2 -- -- 10000 10000 -- -- -- -- 52 35 -- -- -- -- -- -- 50 Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 6 7 20 3 4
11
HM5164405A Series, HM5165405A Series
Read Cycle
HM5164405A/HM5165405A -5 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time Symbol Min Max t RAC t CAC t AA t OEA t RCS t RCH t RCHR t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD t OHR t OFR t WEZ t WED t RDD -- -- -- -- TBD TBD TBD TBD -6 Min Max -- -- -- -- 0 0 60 0 30 18 0 3 3 -- -- 15 3 -- -- 15 15 60 15 30 15 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- -7 Min Max -- -- -- -- 0 0 70 0 35 23 0 3 3 -- -- 18 3 -- -- 18 18 70 18 35 18 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 19 13, 19 13 5 12 12 8, 9 9, 10, 16 9, 11, 16 9
TBD -- TBD -- TBD -- TBD -- TBD -- TBD -- TBD -- TBD -- TBD -- -- -- TBD TBD
TBD -- TBD -- -- -- TBD TBD
TBD -- TBD --
12
HM5164405A Series, HM5165405A Series
Write Cycle
HM5164405A/HM5165405A -5 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol Min Max t WCS t WCH t WP t RWL t CWL t DS t DH TBD -- TBD -- TBD -- TBD -- TBD -- TBD -- TBD -- -6 Min Max 0 10 10 10 10 0 10 -- -- -- -- -- -- -- -7 Min Max 0 13 10 13 13 0 13 -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns 14
Read-Modify-Write Cycle
HM5164405A/HM5165405A -5 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol Min Max t RWC t RWD t CWD t AWD t OEH TBD -- TBD -- TBD -- TBD -- TBD -- -6 Min Max 149 -- 78 33 48 15 -- -- -- -- -7 Min Max 175 -- 91 39 56 18 -- -- -- -- Unit Notes ns ns ns ns ns 14 14 14
Refresh Cycle
HM5164405A/HM5165405A -5 Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol Min Max t CSR t CHR t WRP t WRH t RPC TBD -- TBD -- TBD -- TBD -- TBD -- -6 Min Max 5 10 0 10 0 -- -- -- -- -- -7 Min Max 5 10 0 10 0 -- -- -- -- -- Unit Notes ns ns ns ns ns
13
HM5164405A Series, HM5165405A Series
EDO Page Mode Cycle
HM5164405A/HM5165405A -5 Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hold time from CAS low CAS hold time referred OE CAS to OE setup time Read command hold time from CAS precharge OE precharge time Symbol Min Max t HPC t RASP t CPA t CPRH t DOH t COL t COP t RCHC TBD -- -- -- TBD TBD -6 Min Max 25 -- -- 35 3 10 10 35 10 10 -- -7 Min Max 30 -- Unit Notes ns 18 15 9, 16
100000 -- 35 -- -- -- -- -- -- -- -- 40 3 13 10 40 10 10
100000 ns 40 -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns
TBD -- TBD -- TBD -- TBD -- TBD -- TBD -- TBD --
9, 16
Write pulse width during CAS precharge t WPE t OEP
EDO Page Mode Read-Modify-Write Cycle
HM5164405A/HM5165405A -5 Parameter EDO page mode read- modify-write cycle time WE delay time from CAS precharge Symbol Min Max t HPRWC t CPW TBD -- TBD -- -6 Min Max 68 54 -- -- -7 Min Max 79 62 -- -- Unit Notes ns ns 14
Refresh (HM5164405A Series)
Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 64 128 Unit ms ms Notes 8192 cycles 4096 cycles
Refresh (HM5165405A Series)
Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 64 128 Unit ms ms Notes 4096 cycles 4096 cycles
14
HM5164405A Series, HM5165405A Series
Self Refresh Mode (L-version)
HM5164405AL/HM5165405AL -5 Parameter RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (self refresh) Symbol t RASS t RPS t CHS Min -6 -7 Max Unit -- s -- -- ns ns Notes
Max Min Max Min 100 110 -50 -- -- -- 100 130 -50
TBD -- TBD -- TBD --
Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t RASP defines RAS pulse width in EDO page mode cycles. 16. Access time is determined by the longest among t AA , t CAC and t CPA. 17. All the V CC and VSS pins shall be supplied with the same voltages. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2).
15
HM5164405A Series, HM5165405A Series
20. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH and between tOFR and t OFF. 21. t CSH (min) can be achieved when tRCD tCSH (min) - tCAS (min). 22. Please do not use tRASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS > 100 s, then RAS precharge time should use tRPS instead of tRP. 23. CBR burst refresh or 4096 cycles of distributed CBR refresh with 15.6 s interval should be executed within 64 ms immediately after exiting from and before entering into the self refresh mode. 24. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 25. XXX: H or L (H: V IH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL.
16
HM5164405A Series, HM5165405A Series
Timing Waveforms*25
Read Cycle
t RC t RAS t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
CAS
t RAD t ASR t ASC t RAL t CAL t CAH
t RAH
Address
Row
Column t RRH t RCHR t RCS t RCH
WE t WED t DZC t CDD t RDD Din High-Z
t DZO
t OEA
t OED
OE t OEZ t OHO t OFF t OH t OFR t OHR t WEZ Dout Dout
t CAC t AA t RAC t CLZ
17
HM5164405A Series, HM5165405A Series
Early Write Cycle
t RC t RAS t RP
RAS t CSH t RCD tT CAS t RSH t CAS t CRP
t ASR
t RAH
t ASC
t CAH
Address
Row
Column
t WCS
t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z*
* t WCS
t WCS (min)
18
HM5164405A Series, HM5165405A Series
Delayed Write Cycle*18
t RC t RAS
t RP
RAS t CSH t RCD tT CAS t ASR t RAH t ASC t CAH t RSH t CAS t CRP
Address
Row
Column t CWL t RCS t RWL t WP
WE
t DZC
t DS
t DH
Din
High-Z
Din t OEH t OED t OEP
t DZO

OE t OEZ t CLZ Dout High-Z Invalid Dout
19
HM5164405A Series, HM5165405A Series
Read-Modify-Write Cycle*18
t RWC t RAS
t RP
RAS tT t RCD t CAS t CRP
CAS t RAD t ASR t RAH t ASC t CAH
Address
Row t RCS
Column t CWD t AWD t RWD tCWL t RWL t WP
WE t DZC t DS Din
High-Z Din
t DH
t DZO
t OED t OEA
t OEH t OEP
OE t CAC t AA t RAC t OEZ t OHO
High-Z
Dout t CLZ
Dout
20
HM5164405A Series, HM5165405A Series
RAS-Only Refresh Cycle
t RC t RAS RAS tT t CRP CAS t RPC t CRP t RP
t ASR Address t OFR t OFF Dout Row
t RAH
High-Z
21
HM5164405A Series, HM5165405A Series
CAS-Before-RAS Refresh Cycle
t RC t RP RAS t RPC CAS t CSR tT t CHR t RPC t CRP t RAS t RP
,
t CP t WRP t WRH t CP WE Address t OFR t OFF Dout High-Z 22
HM5164405A Series, HM5165405A Series
Hidden Refresh Cycle
t RC t RAS
t RP
t RC t RAS
t RC t RP t RAS t RP
RAS tT t RSH t RCD t CHR t CRP
CAS
t RAD t ASR t RAH Address Row t ASC t RAL t CAH
Column
t RCS WE
t RRH t RCH
t DZC High-Z Din
t WED t CDD t RDD
t DZO t OEA OE t CAC t AA t RAC t CLZ Dout Dout t OFR t OHR
t OED
t OFF t OH
t OEZ t WEZ t OHO
23
HM5164405A Series, HM5165405A Series
EDO Page Mode Read Cycle (1)
t RP
RAS
t RASP tT t CSH t CAS t RCS t RCHR t RCH t RCS t CP t HPC t CAS t CP t HPC tCAS t RCHC
t HPC t CPRH t CP t t CRP
RSH
CAS
tCAS t RRH t RCH
WE
tASR
Address
tRAH tASC Row
tCAH
t WPE t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
Column 1 t CAL tDZC
t CAL tRDD tCDD
Din
High-Z tDZO tCOL t OEP tOEP tCOP tOED

OE
tOEA
tCPA
tCPA
tCAC tAA
tAA tCAC
tOEZ
tWEZ
tOHO
tCPA tAA tCAC
tAA
tOEZ
tOFR tOHR tOEZ
tCAC
tRAC
tOEA
tDOH
tOHO
tOEA
tOHO tOFF tOH
Dout
Dout 1
Dout 2
Dout 2
Dout 3
Dout 4
24
HM5164405A Series, HM5165405A Series
EDO Page Mode Read Cycle (2)
t RP RAS tT CAS t RCS
WE
t RASP t HPC t CAS tHPC t CP t CAS t RCHC t CP t HPC tRSH tCAS t RRH t RCH t CRP
t CSH t CAS
t CP
tASR
Address
tRAH tASC Row
tCAH
t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
Column 1 t CAL
tDZC
t CAL
tRDD tCDD
Din
High-Z tDZO tCOL t OEP tOEP tCOP tOED

OE
tOEA
tCPA
tCAC tAA
tAA tCAC
tOEZ
tOHO
tCPA tAA tCAC
tCPA
tAA
tOEZ
tOFR tOHR tOEZ
tRAC
tDOH
tOEA
tCAC
tDOH
tOHO
tOEA
tOHO tOFF tOH
Dout
Dout 1
Dout 2
Dout 2
Dout 3
Dout 4
25
HM5164405A Series, HM5165405A Series
EDO Page Mode Early Write Cycle
t RASP
t RP
RAS tT t CSH t RCD t CAS CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
t ASR t RAH
t ASC
t CAH
t ASC
tCAH
t ASC t CAH
Address
Row
Column 1
Column 2
Column N
t WCS
t WCH
t WCS
t WCH
t WCS
t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din 1
Din 2
Din N
Dout
High-Z*
* t WCS
t WCS (min)
26
HM5164405A Series, HM5165405A Series
EDO Page Mode Delayed Write Cycle*18
t RASP t RP RAS tT t CSH t RCD
CAS
t CP t CAS t HPC t CAS
t CP t RSH t CAS
t CRP
t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t WP t DZC t DS t DH Din 2 t DZO t OED t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL

t OEP t OEP t OEP
t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout High-Z
Invalid Dout Invalid Dout Invalid Dout
27
HM5164405A Series, HM5165405A Series
EDO Page Mode Read-Modify-Write Cycle*18
t RASP t RP RAS tT t CP t RCD
CAS
t HPRWC t CP t CAS t CAS
t RSH t CAS
t CRP
t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO
t OED
t ASC t CAH Column 2 t CWL t RCS t CPW t AWD t CWD t RCS t CWL
t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL
Address
t WP t DZC t DS t DH Din 2 t OED
t WP t DZC t DS t DH Din N t OED
Din 1
t OEP
t OEH
t DZO
t OEP
t OEH
t DZO
t OEP
t OEH
*
OE t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ
High-Z
Dout
Dout 1
Dout 2
Dout N
28
HM5164405A Series, HM5165405A Series
EDO Page Mode Mix Cycle (1)
t RP
RAS
t RASP t CRP tCAS tRSH t RCS tCPW tAWD t ASC tRAH Row tCAH t ASC t CAH Column 2 t CAL tASC t CAH Column 3 t CAL t DS High-Z tOED t DH Din 3 t OEP tWED tWP t RAL t CAH Column 4 t CAL tRDD tCDD t RCS t RRH t RCH
tT
CAS
t CP t CAS t CSH t RCD t WCS t WCH t CAS
t CP tCAS
t CP
WE
tASR
Address
tASC
Column 1 t CAL
t DS
Din
t DH Din 1

OE
tCPA tAA tOEA
tCPA
tCPA tAA
t OEZ
tAA
tOFR tWEZ tOEZ
tCAC
tOHO tOFF tOH
tCAC
t DOH
tCAC t OHO
tOEA
Dout
Dout 2
Dout 3
Dout 4
29
HM5164405A Series, HM5165405A Series
EDO Page Mode Mix Cycle (2)
t RP
RAS
t RASP
tT
CAS
t CSH t CAS t RCD t RCS t RCHR
t CP t CAS
t CP tCAS
t CP tCAS t RCS tCPW tWP t RAL tASC t CAH Column 4 t CAL t DS t DH Din 3 t OEP tOED tCOP tRSH
t CRP
t RCH tWCS t WCH
t RCS
t RRH t RCH
WE
tASR
Address
tRAH Row
t ASC
tCAH
t ASC t CAH Column 2 t CAL t DS t DH Din 2 t OEP tOED tCOL
t ASC t CAH Column 3 t CAL
Column 1 t CAL
tRDD tCDD
Din
High-Z
tWED
OE
tAA tOEA tCAC tRAC t OHO
Dout
t OEA tOEZ tCPA tAA tCAC tOEZ t OHO
Dout 3
tCPA tAA tCAC tOEA
tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4
Dout 1
30
HM5164405A Series, HM5165405A Series
Self Refresh Cycle (L-version)* 22, 23, 24
t RP
t RASS
t RPS
RAS t RPC tT t CRP t CHS
, ,
t CP t CSR CAS t WRP WE t OFR t OFF Dout
t WRH
, + & $
High-Z 31
HM5164405A Series, HM5165405A Series
Package Dimensions
HM5164405AJ/ ALJ Series HM5165405AJ/ ALJ Series (CP-32DC)
Unit: mm
32
20.95 21.38 Max
17 10.16 0.12
+0.12 -0.13
1
+0.25 -0.24
0.74
16 0.64 Min 3.50
11.18
0.43
+0.07 -0.04
1.27 0.10
9.40 0.25
32
2.55
HM5164405A Series, HM5165405A Series
HM5164405ATT/ALTT Series HM5165405ATT/ALTT Series (TTP-32DC)
Unit: mm
20.95 21.35 Max 32 17
1
+0.08 -0.07
1.27 0.20
M
16 11.76 0.20
0.42
10.16
1.20 Max
0.145
0.08 Min 0.18 Max
0 - 5
+0.03 -0.02
0.10 1.15 Max
0.50 0.10
0.68
33
HM5164405A Series, HM5165405A Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
34
HM5164405A Series, HM5165405A Series
Revision Record
Rev. 0.0 0.1 Date Oct. 13, 1995 Apr. 30, 1996 Contents of Modification Initial issue Change format Unification of HM5164405A Series and HM5165405A Series Addition of HM5164405A/HM5165405A-5 Series Addition of HM5164405AJ/ALJ Series, HM5165405AJ/ALJ Series (CP-32DC) Pin Descriptions Addition of Row/Refresh address and Column address to address input Addition of Block Diagrams DC Characteristics (HM5165405A) I CC1 max: 140/130 mA to TBD/180/160 mA I CC3 max: 120/105 mA to TBD/180/160 mA I CC6 max: 120/105 mA to TBD/150/130 mA I CC7 max: 120/105 mA to TBD/140/120 mA Addition of note 4 AC Characteristics t RCD max: 38/45 ns to TBD/45/52 ns t COP min: 5/5 ns to TBD/10/10 ns Addition of t WPE and tOEP t HPRWC min: 79/90 ns to TBD/68/79 ns Addition of notes 20 to 24 Change of notes 3 and 13 Timing waveforms Addition of t WPE and tOEP timings Deletion of note: t OEH tCWL 0.2 Jun. 12, 1996 AC Characteristics Change of notes 18 and 25 Timing waveforms Deletion of notes about undefined pins Drawn by S. Ikenaga S. Ikenaga Approved by J. Kitano J. Kitano
35

▲Up To Search▲

Price & Availability of 5164405A

	To Download 5164405A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .